1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method to read flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices that reduces the stress in the tunnel oxide in the source region.
2. Discussion of the Related Art
A microelectronic Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting select transistors that would enable the cells to be erased independently. As a result all of the cells must be erased simultaneously as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary "1" or "0" or to erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together to a common source. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying typically 8-9 volts to the control gate, approximately 5 volts to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell can be erased in several ways. In one arrangement, applying typically 12 volts to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can erase a cell.
The cell is read by applying typically 4 to 5 volts to the control gate, approximately 1 volt or less to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (.apprxeq.4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (.apprxeq.2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
To have high enough read current, the voltage at the gate is required to be 4 to 5 volts. Because the source is grounded (0 volts), this relatively large potential difference across the tunnel oxide in the vicinity of the source region. The relatively large potential difference causes a stress field across the tunnel oxide in the vicinity of the source region during the duration of the read pulse. This field is applied across all the bits on the selected wordline. Due to oxide integrity weakness from bit-to-bit, some bits will gain charge and disturb the state of the bits. Blank "1" cells could be programmed and turn to a "0" causing a failure of the flash device after many read cycles. The field across the tunnel oxide is highest close to the source junction. The tunnel "thin" oxide at the source side experiences most of the degradation during cycling, becoming weak allowing conduction through it at lower applied electric fields.
Because the source junction is more graded than the drain junction and optimized for erase, higher voltages across the source could be used without enhancing read disturb due to hot-carrier injection. Reading the cell at the source side reduces the field across the weakest or stressed region of the tunnel oxide during read. For example, if the cell is read with 2 volts applied to the source, the stress across the tunnel oxide will be significantly reduced relative to the conventional approximately 1.7 Megavolts per centimeter. This reduction in the oxide field will result in extending the time-to-failures of flash devices by better than an order of magnitude. This method will work the best for applications with reduced source capacitance, for example, a device with a local interconnect. In addition, the time required to pump the source voltage during page read becomes insignificant for the devices having high V.sub.ss capacitance.
Therefore, what is needed is a method of reading a cell that reduces the stress across the tunnel oxide at the source region.